The present invention relates to an analog to digital (A/D) converter, and, more particularly, to an A/D converter including an encoder.
A/D converters are often used with microprocessors to convert an analog signal to a corresponding digital signal which is processed by the microprocessor. Due to the increased speed of microprocessors, for example, from 50 MHZ to 300 MHZ, there is a need for faster A/D converters. A/D converters of the parallel type and the serial and parallel type are advantageous for high speed operation. Such A/D converters generally comprise a plurality of comparators for comparing an analog input signal with analog reference voltages and an encoder for converting output signals of the comparators to a multibit digital signal. The speed and accuracy of the A/D converter can be improved by increasing the speed and accuracy of the encoder.
A conventional, parallel-type A/D converter comprises a comparator section, a logical boundary detection section for detecting a logical boundary of comparator output signals and an encoder section. The encoder section often includes a wired-OR type ROM. Referring to FIG. 1, a first example of a conventional parallel-type A/D converter which outputs a five (5) bit digital signal is shown. The A/D converter comprises a comparator section 1 having comparators CM1 to CM31 and associated resistors R, a logical boundary detection section 2 having NOR circuits DE0 to DE31, and an encoder section 3a having ROM cells 4.
Between a high potential side reference voltage VRH and a low potential side reference voltage VRL, thirty two resistors are connected in series. The two resistors R positioned on opposite ends of the series connection have a resistance value equal to half that of the other resistors R. A junction between each adjacent one of the resistors R is connected to a first input terminal of a corresponding one of 31 comparators CM1 to CM31. A voltage difference between the reference voltages VRH and VRL is divided by the resistors R, and reference voltages VR1 to VR31 obtained by the division are input to the comparators CM1 to CM31, respectively. An analog input signal Ain is input to second terminals of the comparators CM1 to CM31. The comparators CM1 to CM31 compare the analog input signal Ain with the reference voltages VR1 to VR31, in response to a control signal output from a control circuit (not shown).
Each of the comparators CM1 to CM31 outputs an output signal S1 to S31 high and an output signal /S1 to /S31 low when the potential of the analog input signal Ain is lower than the reference voltage VR1 to VR31. On the other hand, when the potential of the analog input signal Ain is higher than the reference voltage VR1 to VR31, each of the comparators CM1 to CM31 outputs an output signal S1 to S31 low and an output signal /S1 to /S31 high.
For example, if the potential of the analog input signal Ain is higher than the reference voltage VR4 but lower than the reference voltage VR5, then the comparators CM1 to CM4 output thermometer code bits wherein the output signals S1 to S4 have L levels and the output signals /S1 to /S4 have H levels. Meanwhile, the comparators CM5 to CM31 output thermometer code bits wherein the output signals S5 to S31 have H levels and the output signals /S5 to /S31 have L levels.
Each of the output signals S1 to S31 of the comparators CM1 to CM31 is input to a first terminal of a corresponding one of the NOR circuits DE1 to DE31 while each of the output signals /S1 to /S31 of the comparators CM1 to CM31 is input to a second input terminal of a corresponding one of the NOR circuits DE0 to DE30. Further, one of a pair of terminals of each of the NOR circuits DE0 and DE31 is connected to the ground GND. Each of the NOR circuits DE0 to DE31 outputs a signal high if both of the input signals thereto have L levels, and only one of the NOR circuits DE0 to DE31 outputs a signal high by operation of the comparators CM1 to CM31. The output signals of the NOR circuits DE0 to DE31 are output to word lines WL0 to WL31, respectively.
The encoder section 3a includes five bit lines BL0 to BL4 corresponding to a 5-bit digital output signal B0 to B4. ROM cells 4 for outputting the output signal B0 to B4 in the form of a binary code are connected at predetermined locations between the word lines WL0 to WL31 and the bit lines BL0 to BL4. Each of the ROM cells 4 comprises an N-channel MOS transistor, shown in FIG. 2. The gate of the transistor is connected to one of the word lines WL and the drain is connected to one of the bit lines BL while the source is connected to the ground GND.
The bit lines BL0 to BL4 are connected to a power supply VDD through switch circuits SW0 to SW4, respectively, such that, when the switch circuits SW0 to SW4 are closed, the bit lines BL0 to BL4 are precharged. Each of the switch circuits SW0 to SW4 preferably comprises a P-channel MOS transistor.
If the level of one of the word lines changes to an H level after the switch circuits SW0 to SW4 are opened, then ROM cells connected to the activated word line are turned on and the levels of the bit lines which are connected to the ROM cells are changed to an L level. For example, if the level of the word line WL0 is changed to an H level, then the output signals B0 to B4 are xe2x80x9c00000xe2x80x9d; and if the level of the word line WL2 is changed to an H level, then the output signals B0 to B4 are xe2x80x9c01000xe2x80x9d.
Since the encoder section 3a employs a ROM circuit which requires a precharging operation, the operation speed of the comparator section 1 is lower than the operation speed of the encoder section 3a. Accordingly, the conversion speed is determined by the comparator section 1.
The output signals of the comparator section 1 in normal operation either are a thermometer code which exhibits only one logical boundary or exhibit the same logic value. However, a babble error sometimes occurs with a thermometer code. The babble error which occurs probabilistically most frequently is reversal of one output logic value in the output signals /S1 to /S31 of the comparators CM1 to CM31. If such a babble error is input to the NOR circuits DE0 to DE31, then two word lines exhibit H levels simultaneously, and an incorrect output signal B0 to B4 is output.
Particularly, the encoder section 3a constructed to output a binary code, sometimes has a large error due to a babble error. In particular, if the word lines WL14 and WL16 shown in FIG. 3 exhibit H levels simultaneously due to a babble error, then the output signal B0 to B4 are all zero and a large error occurs with the output signal B0 to B4.
In order to solve such a problem, an A/D converter having a modified logical boundary detection section 2, as shown in FIG. 4, has been proposed. Referring to FIG. 4, the A/D converter is constructed such that the NOR circuits DE0 to DE31 have 3-input terminals. If an nth NOR circuit is represented as NOR circuit DEn, an output signal Sn of the comparators CMn and output signals /S(n+1) and /S(n+2) of two higher order comparators CM(n+1) and CM(n+2) are input to the NOR circuit DEn. When a babble error (a different logic value is included in a thermometer code) occurs, the babble error location is not discriminated as a logical boundary, and only one of the word lines WL exhibits H levels and an output signals B0 to B4 having correct values or values near to correct values are output.
However, even where the NOR circuits DE0 to DE31 have 3-inputs, if, for example, such a babble error that an output logic value spaced by a two or more logic value distance is reversed, then two word lines spaced by a two word line distance exhibit an H level simultaneously. If, for example, the word lines WL14 and WL17 shown in FIG. 3 simultaneously exhibit H levels, then the output signals B0 to B4 are all zero, which is a large error.
In order to solve the disadvantage, an A/D converter which includes an encoding section 3b which outputs a Gray code (reflected binary code) in place of a binary code has been proposed.
Referring to FIG. 5, the encoding section 3b is different from the encoder section 3a which outputs a binary code in terms of the positions of the ROM cells 4. That is, the encoding section 3b outputs signals G0 to G4 of a Gray code wherein one of the word lines WL exhibits an H level. Where a thermometer code is recognized as a decimal number (Decimal), a corresponding relationship between the output signals B0 to B4 of a binary code (Binary) and the output signals G0 to G4 of a Gray code (Gray) corresponding to a thermometer code is illustrated in FIG. 9. The output signals G0 to G4 are output to a next stage circuit through a conversion circuit which converts a Gray code into a binary code.
In such an A/D converter, even if a babble error is output from the comparator section 1 and the logical boundary detection section 2 outputs an H level, for example, to the word lines WL14 and WL17 in FIG. 6 simultaneously, the encoding section 3b outputs the output signals G0 to G4 same as that only when the word line WL14 exhibits an H level. Accordingly, even if a most likely value is provided when the word line WL15 or the word line WL16 exhibits an H level, the encoder section 3b does not output signals having large errors.
Thus, if a babble error occurs with an output signal of the comparator section 1, an error is suppressed, as shown in FIGS. 12 to 14.
FIG. 12 illustrates operation when a babble error xe2x80x9c . . . 11101000 . . . xe2x80x9d (type b1), wherein an output logic value of a thermometer code spaced by a one logic value distance is reversed, is input to the logical boundary detection section 2 having 2-input NOR circuits, and output signals of the logical boundary detection section 2 are converted into a Gray code by the encoding section 3b. The abscissa indicates a decimal value of a normal thermometer code while the ordinate is a value obtained by converting an output signal of a Gray code output from the encoding section 3b to a decimal number.
FIG. 13 illustrates operation when a babble error xe2x80x9c . . . 111001000 . . . xe2x80x9d (type b2H), wherein an output logic value of a thermometer code spaced by a two logic value distance is reversed, is input to the logical boundary detection section 2 having 3-input NOR circuits, and output signals of the logical boundary detection section 2 are converted into a Gray code by the encoding section 3b. The abscissa and the ordinate are the same as FIG. 12.
FIG. 14 illustrates operation when a babble error xe2x80x9c . . . 111011000 . . . xe2x80x9d (type b2L), wherein an output logic value of xe2x80x9c1xe2x80x9d of a thermometer code spaced by a two logic value distance is reversed to xe2x80x9c0xe2x80x9d, is input to the logical boundary detection section 2 having 3-input NOR circuits, and output signals of the logical boundary detection section 2 are converted into a Gray code by the encoding section 3b. The abscissa and the ordinate are the same as FIG. 12.
Since the encoding section which outputs a Gray code suppresses an error, as opposed to the encoding section which outputs a binary code, it is advantageous. However, conversion circuit for converting a Gray code to a binary code is required. However, an error is still generated with respect to a value which is considered to be most likely.
Accordingly, yet another A/D converter has been proposed wherein logical processing by a majority decision circuit is performed for a thermometer code output from the comparator section. However, employment of the majority decision circuit increases the circuit scale of the A/D converter. Therefore, in order to suppress an increase in circuit scale, it has been proposed to form the majority decision circuit from an analog circuit (J. van de Valburg and R. J. van de Plassche, xe2x80x9cAn 8-bit 650-MHZ folding ADCxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 27, pp. 1662-1666, December 1992). However, even an analog majority decision circuit does not exhibit a sufficient effect against a babble error of the type b2H or the type b2L wherein an output logic value spaced by a two logic value distance is inverted.
An A/D converter having an irregular decoding logic for the logic boundary detection section is also been proposed, so that, even if a babble error occurs, a most likely digital output signal is output (C. W. Mangelsdorf, xe2x80x9cA 400-MHZ Input Flash Converter with Error Correctionxe2x80x9d, Journal of Solid-State Circuits, Vol. 25, pp.184-191, February 1990). Another A/D converter wherein logical boundary detection is performed for upper bits and lower bits into which the thermometer code is divided instead of performing logical boundary detection between adjacent outputs of a thermometer code (Y. Gendai et al., xe2x80x9cAn 8b 500-MHZ ADCxe2x80x9d, Digest of International Solid-State Circuit Conference, TPM 10.5, pp.29-35, February 1991), has been proposed, and a further A/D converter wherein the logical boundary detection section performs logical comparison of a thermometer code for every other bit to suppress production of a babble error (A. Matsuzawa et al., xe2x80x9cAn 8b 600-MHZ Flash A/D with multistage duplex gray codingxe2x80x9d, Symp. VLSI Circ. Dig. Tech. Papers, pp.37-42, May 1991) has been proposed. These A/D converters eliminate or correct a babble error produced in a thermometer code by the logical boundary detection section.
In contrast, an A/D converter of the twin encoder type is available wherein a babble error is corrected by the encoder section. In the A/D converter, an average of output signals of an encoder comprising P-channel MOS transistors and another encoder comprising N-channel MOS transistors is calculated (M. Ito et al., xe2x80x9cA 10-bit 20 MS/s 3 V Supply CMOS AD Converterxe2x80x9d, 1994 Journal of Solid-State Circuits, Vol. 25, pp.1531-1536, February 1990). However, using the design, the circuit scale of the encoder is doubled.
Also an A/D converter having a reduced number of logic stages of a conversion circuit for converting a Gray code into a binary code is available, in which an encoder outputs a Quasi Gray code so that the operation speed of the encoder is improved (Y. Akazawa, xe2x80x9cA 400 MSPS 8b Flash A/D Conversion LSIxe2x80x9d, ISSCC Digest of Technical Papers, pp.98-99, February 1987).
The encoding sections of the A/D converters of the parallel type are all constructed in the form of a ROM using wired OR gates. In this construction, a precharging operation is required for each operation cycle, and the precharging operation requires approximately half of one cycle. Thus, the precharge time requirement makes it difficult to improve the operation speed of the encoding section.
Further, since the encoding section does not function to correct an error caused by a babble error which occurs in a thermometer code, correction of a babble error is performed principally by the logical boundary detection section. However, even if an encoding section which outputs a Gray code which has a comparatively low degree in error is used, an error of an output signal by a babble error is not fully removed.
High speed A/D converters having conversion speeds exceeding 10 MS/s (Mega Sample/sec) are used not only for image processing, but recently, for data reading apparatus, such as a hard disk drive, and also for high speed data communication devices using QPSK (Quadrature Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). Accordingly, conversion speeds exceeding 100 MS/s and an error rate exceeding 10xe2x88x9210 are required. Consequently, a performing test of an A/D converter which operates at a high speed must performed with certainty.
An A/D converter is performance tested by connecting the A/D converter to a testing apparatus. Then, a clock signal and an analog input signal are input from the testing apparatus to the A/D converter. The A/D converter samples the analog input signal in response to the clock signal, converts the sampled analog signal into a digital signal and outputs the digital signal to the testing apparatus. The testing apparatus evaluates the digital signal output from the A/D converter to determine whether it meets its performance specifications.
With an increase in operation speed of an A/D converter, an increase in frequency of a clock signal and an analog input signal input from the testing apparatus is required. In a performance test, the clock signal supplied from the testing apparatus is required to have a frequency two or three times as high as that in ordinary use, and the analog input signal is required to be input with a frequency higher than xc2xc that of the clock signal.
Although, the testing apparatus can supply such a high frequency, it is difficult to produce a corresponding high speed analog signal. Also it is difficult to deliver a digital signal output in a high speed cycle from an A/D converter to a testing apparatus to evaluate it, such that present testing apparatus do not perform adequately.
It is a first object of the present invention to provide an encoder which has a function of correcting a babble error included in a thermometer code input thereto and also has an improved operation speed.
It is a second object of the present invention to provide a testing method which adequately performs a performance test of a high speed A/D converter.
Briefly stated, the present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal having a phase which varies successively with respect to the sampling clock signal; and an A/D converter for sampling the analog signal in accordance with the sampling clock signal to generate a digital signal. The A/D converter includes: a comparator section for receiving the analog signal and generating a corresponding thermometer code; an encoder section for receiving the thermometer code, detecting a logical boundary of the thermometer code, and producing a corresponding gray code digital signal therefrom; and a gray code to binary code conversion section for converting the gray code to a binary code.
The present invention provides an encoder for encoding a thermometer code including: an encoder circuit for detecting a logical boundary of the thermometer code to produce a Gray code signal, wherein the Gray code signal comprises a lower order bit and an upper order bit, and a particular relationship is set between the lower order bit and the upper order bit when the Gray code signal is error free; an error detector circuit, coupled to the encoder circuit, for detecting whether the particular relationship is satisfied and generating an error bit signal when the particular relationship is not satisfied; an error correction circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and generating a corrected bit signal; and a Gray to binary converter circuit connected to the error correction circuit for converting the Gray code signal including the corrected bit signal into a binary code signal.
The present invention provides an encoder for encoding a thermometer code including: an encoder circuit for detecting a logical boundary of the thermometer code to produce a Gray code signal including an upper bit and decomposed lower order bits regarding a lower order bit of the Gray code, wherein a particular relationship is set between the upper bit and the decomposed lower order bits when the Gray code in error free; an error detector circuit, coupled to the encoder circuit, for detecting whether the particular relationship between the lower order and upper order bits is satisfied and generating an error bit signal when the particular relationship is not satisfied; and a Gray to binary converter circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and converting the Gray code signal including corrected bit signal into a binary code signal.
The present invention provides a method of converting a Gray code to a binary code, the Gray code including a plurality of decomposed Gray code bits. The method includes the steps of: logically processing the plurality of decomposed Gray code bits to produce a plurality of binary code bits for one bit of the binary code; and logically processing the plurality of binary code bits to produce one bit of the binary code.
The present invention provides an apparatus for converting a Gray code to a binary code, the Gray code including decomposed Gray code bits. The apparatus includes: a first logic circuit for logically processing the plurality of decomposed Gray code bits to produce a plurality of binary code bits for one bit of the binary code; and a second logic circuit for logically processing the plurality of binary code bits to produce one bit of the binary code.
The present invention provide an A/D converter including: a plurality of comparators for receiving and comparing an analog input voltage with reference voltages different from each other and producing a thermometer code based upon the comparison results; a logical boundary detector, coupled to the comparators, for detecting a logical boundary of the thermometer code and outputting a logical boundary detection signal; and an encoder coupled to the logical boundary detector for receiving the logical boundary detection signal and generating a binary code signal. The encoder includes: an encoder circuit for receiving the logical boundary detection signal to produce a Gray code signal, wherein the Gray code signal comprises a lower order bit and an upper order bit, and a particular relationship is set between the lower order bit and the upper order bit when an error code bit is not included in the Gray code; an error detector circuit coupled to the encoder circuit for detecting whether the particular relationship between the lower order and upper order bits is set and generating an error bit signal when the particular relationship is not satisfied; an error correction circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and generating a corrected bit signal; and a Gray to binary converter circuit for converting the Gray code signal including the corrected bit signal into a binary code signal.
The present invention provides an error correction method for an encoded signal including a thermometer code. The method includes the steps of: detecting a logical boundary of the thermometer code; producing, based on the detected logical boundary, a Gray code including a lower order bit and an upper order bit, wherein a particular relationship is set between the lower order bit and the upper order bit when an error code bit is not included in the Gray code; determining whether the particular relationship is satisfied; and correcting an error code bit included in the Gray code using a predetermined error code processing procedure when the particular relationship is not satisfied.
The present invention provides an error correction method for an encoded signal including a thermometer code. The method includes the steps of: detecting a logical boundary of the thermometer code; producing, based on the detected logical boundary, a Gray code including a lower order bit and an upper order bit; dividing the lower order bit into a front lower order bit of a logical target and a back lower order bit of a non-logical target; decomposing the front lower order bit into decomposed front lower order bits and decomposing the back lower order bit into decomposed back lower bits, so that a particular relationship is set between the decomposed front and back lower order bits and the upper order bit when an error code bit is not included in the Gray code; determining whether the particular relationship is satisfied; and correcting an error code bit included in the Gray code using a predetermined error code processing procedure when the particular relationship is not satisfied.
The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code includes a lower order bit and an upper order bit, which have a particular relationship set therebetween. The computer readable program performs the steps of: detecting whether the particular relationship is satisfied; and correcting an error code bit included in the Gray code when the particular relationship is not satisfied.
The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code has a lower order bit and an upper order bit. The lower order bit includes a logical target lower order bit and a non-logical target lower order bit. The computer readable program performs the steps of: decomposing at least one of the logical and non-logical target lower order bits to generate decomposed Gray code; comparing the decomposed Gray code with the upper order bit to detect an error code bit; and correcting the error code bit included in the Gray code.
The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code has a lower order bit and an upper order bit. The lower order bit includes a logical target lower order bit and a non-logical target lower order bit. The computer readable program performs the steps of: decomposing at least one of the logical and non-logical target lower order bits to generate decomposed lower order bits; comparing the decomposed lower order bits with the upper order bit to detect an error code bit; and correcting the error code bit included in the Gray code.
The present invention provides a recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code. The Gray code has a lower order bit and an upper order bit. The lower order bit includes a logical target lower order bit and a non-logical target lower order bit. The computer readable program performs the steps of: decomposing at least one of the logical and non-logical target lower order bits to generate decomposed lower order bits; comparing the decomposed lower order bits with the upper order bit to detect an error code bit; correcting the error code bit included in the Gray code by inverting the error code bit; and converting the Gray code including the corrected code bit into a binary code.
The present invention provides a recording medium having recorded thereon a computer readable program code for detecting a logical boundary of a thermometer code. The computer readable program performs the steps of: inputting three or more every other bits of a thermometer code; and successively comparing the three or more every other bits of the thermometer code to detect the logical boundary of the thermometer code.
The present invention provides a testing method for an A/D converter including the steps of: detecting a logical boundary of a thermometer code to produce a Gray code including a lower order bit and an upper order bit which have a particular relationship; determining whether the particular relationship is satisfied; generating an error signal when the particular relationship is not satisfied; detecting whether an error code is included in the thermometer code based on the error signal.
The present invention provides a testing method for an A/D converter operating in accordance with a sampling clock signal. The method includes the steps of: producing an analog signal having a phase which varies successively with respect to the sampling clock signal; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D convertor; and evaluating the digital signal.
The present invention provides a testing method for an A/D converter operating in accordance with a sampling clock signal. The method includes the steps of: producing an analog signal having one of a DC level and amplitude which varies successively with respect to the sampling clock signal; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D converter; and evaluating the digital signal.
The present invention provides a testing method for an A/D converter converting an analog signal to a digital signal. The method includes the steps of: producing a sampling clock signal having a phase which varies successively with respect to the analog signal; sampling the analog signal in accordance with the sampling clock signal to generate the digital signal using the A/D converter; and evaluating the digital signal.
The present invention provides a testing method for an A/D converter including the steps of: producing a sampling clock signal having one of a DC level and amplitude which varies successively with respect to an analog signal; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D converter; and evaluating the digital signal.
The present invention provides a testing method for an A/D converter operating in accordance with a sampling clock signal. The method includes the steps of: producing an analog signal from the sampling clock signal; producing a comparison reference voltage which successively varies; providing the analog signal and the comparison reference voltage to the A/D converter; sampling the analog signal in accordance with the sampling clock signal to generate a digital signal based on the sampled analog signal and the comparison reference voltage using the A/D converter; and evaluating the digital signal.
The present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal having a phase which varies successively with respect to the sampling clock signal; and an A/D converter for sampling the analog signal in accordance with the sampling clock signal to generate a digital signal.
The present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal having one of a DC level and amplitude which varies successively with respect to the sampling clock signal; and an A/D converter for receiving the analog signal and sampling the analog signal in accordance with the sampling clock signal to generate a digital signal.
The present invention provides a semiconductor device including: a clock signal production circuit for receiving an analog signal and producing a sampling clock signal having a phase which varies successively with respect to the analog signal; and an A/D converter for receiving the analog signal and sampling the analog signal in accordance with the sampling clock signal to generate a digital signal.
The present invention provides a semiconductor device including: a clock signal production circuit for receiving an analog signal and producing a sampling clock signal having one of a DC level and amplitude which varies successively with respect to the analog signal; and an A/D converter for receiving the analog signal and sampling the analog signal in accordance with the sampling clock signal to generate a digital signal.
The present invention provides a semiconductor device including: an analog signal production circuit for receiving a sampling clock signal and producing an analog signal; a comparison reference voltage production circuit for producing a comparison reference voltage which successively varies; and an A/D converter for receiving the analog signal and the comparison reference voltage and sampling the analog signal in accordance with the sampling clock signal, the A/D converter further generating a digital signal based on the sampled analog signal and the comparison reference voltage.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.